1. Field
Embodiments of the present invention relate to a processor, an information processing apparatus, and a method of controlling the processor.
2. Description of the Related Art
“Scalable Processor ARChitecture (SPARC)-V9 (Registered Trademark of SPARC International, Inc.)” has been introduced as one of the architectures of a processor, such as a central processing unit (CPU) provided in an information processing apparatus including a server or the like. According to the SPARC Architecture Version 9, sixty four to five hundred twenty eight 64-bit registers may be implemented as general-purpose registers (GPR).
FIG. 11 exemplarily illustrates a register window 1 used as a general-purpose register file provided in the SPARC Architecture Version 9. In FIG. 11, the register window 1 includes eight in-registers (W0 in to W7 in), eight local registers (W0 local to W7 local), and eight out-registers (W0 out to W7 out), which correspond to eight windows, for example. Of the above-described registers, the in-registers and the out-registers overlap one another, that is, the in-register W0 in and the out-register W7 out overlap each other, the in-register W1 in and the out-register W0 out overlap each other, and so forth as illustrated in FIG. 11. Since the in-registers and the out-registers overlap one another, the performance of a procedure call made to call process including a group of processing procedures is increased.
FIG. 12 illustrates an exemplary data-selector circuit provided for the general-purpose register file. In FIG. 12, a general-purpose register file 2 includes four sets of the above-described register-window configuration and eight general-purpose registers (global registers). According to FIGS. 11 and 12, the sum total of the registers becomes 160 (=8 [global]×4 [set]+(8 [local]+8 [inout]×8 [window]). As illustrated in FIG. 12, a readout circuit 3 including a multistage-selector circuit (not shown) is provided. The readout circuit 3 selects, for example, a single register from among the 160 registers and reads data of the selected register. The read data are stored in a source-latch circuit 4 and input to an accumulator 5 including an accumulator.
Incidentally, the method of detecting an error in data by adding a parity bit to data held in a register file and checking the parity bit added to the data has been used as one of methods of detecting a fault in an information processing apparatus. Further, the method of adding an error-correcting code (ECC) to data and correcting the data based on the ECC when an error is detected from the data has been used. For the information processing apparatus including the above described general-purpose register file, there have been demands for detecting an error and correcting data including the detected data.
Hitherto, main memories that were provided with an error-detection method achieved through the parity checking and a data-correction method performed based on the ECC have been available. For example, the main memory includes a plurality of main memory modules including, for example, a dual inline memory module (DIMM) storing data, an error detection-and-correction bit and a parity bit, a main processor configured to process information read from the main storage module, a parity-checking means arranged to perform the parity checking for the information read from the main storage module, and an error detection-and-correction means arranged to detect and correct an error in the information read from the main storage module. When the error is detected through the parity checking, the main processor suspends an information processing operation, and restarts the information processing operation after the error is corrected. Further, there have been information processing apparatuses including a memory holding data with the parity bit, a parity-checking means arranged to perform the parity checking, and an error-correction means arranged to perform the error correction based on error information transmitted from the parity-checking means.
However, since the information processing apparatus including the above described general-purpose register file is provided with multistage-selection logic in a path used to read data from the general-purpose register file, it takes much time to read the data from the general-purpose register file. Therefore, the marginal-operation frequency of a processor may be determined based on the path used to read data from the general-purpose register file. When the error-corrector using the ECC is provided in the above described read path, the time consumed to read data from the general-purpose register file is increased. Thus, it has been difficult to further provide the error-corrector in the read path.
On the other hand, according to the method of suspending the information processing operation and restarting the information processing operation after the error correction is performed, an instruction-controller or the like is informed of an error in read data when the error is detected, and the error-correction processing is performed. Therefore, the time consumed from when the error is detected to when the information processing apparatus returns to an ordinary operation state becomes equal to the sum of the time consumed to perform the error-informing processing and that consumed to perform the error-correction processing, which decreases the performance of the information processing apparatus. Further, since an error-correction state is provided in addition to the normal operation state, the configuration of a circuit controlling the error-correction state becomes complicated, which increases the amount of hardware, that is, the circuit amount.
A processor, an information processing apparatus, and a method of controlling the processor that allow for reducing the time consumed from when an error in read data is detected to when the error is corrected and the processor returns to the ordinary operation state are provided. A processor, an information processing apparatus, and a method of controlling the processor that allow for reducing the hardware amount are provided.
The processor, the information processing apparatus, and the method of controlling the processor allow for reducing the time consumed from when an error in read data is detected to when the error is corrected and the processor returns to the ordinary operation state, and reducing the hardware amount.
Japanese Laid-open Patent Publication No. 9-81465 and Japanese Laid-open Patent Publication No. 5-20215 are examples of related art.